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RISC OS 3.5 is an operating system written by Acorn for its Risc PC computers that use the new ARM600 / ARM700 hardware architecture. This version was only changed where it was necessary to support the changing hardware. RISC OS 3.6 is a further development, which adds support for machines using the similar ARM7500 architecture, and integrates software that was previously separately available. We have tried to make both versions as compatible as possible with the RISC OS 3.1 operating system.
The operating system known as RISC OS 2 in this manual consists of two variants, RISC OS 2.00 and RISC OS 2.01.
The operating system known as RISC OS 3 in this manual consists of two variants, RISC OS 3.00 and RISC OS 3.10.
The operating system known as RISC OS 3.5 in this manual is RISC OS 3.50, and is the version supplied with the first generation of Risc PC computers.
The operating system known as RISC OS 3.6 in this manual is RISC OS 3.60, and is the version supplied with the second generation of Risc PC computers, and the first generation of A7000 computers.
The main electronic components of a Risc PC computer are:
This chip replaces the IOC and MEMC chips used in earlier RISC OS computers.
The main component of the A7000 is the ARM7500 chip; this integrates all the above functionality into a single chip.
The other components are:
The diagram below gives a schematic of an architecture which may be viewed as typical of the Risc PC range of computers.
Schematic of a Risc PC computer
The ARM is a RISC (Reduced Instruction Set Computer) processor. The initial range of Risc PC computers can use two different versions of the ARM processor.
From the application programmer's point of view, there is no difference between the two processors. The ARM700 supports the same instruction set as the ARM610.
It is possible that other chips in the ARM6 / ARM7 family may also be used.
The VIDC20 chip is an updated version of the VIDC1 and VIDC1a chip used in the previous generation of Acorn computers. The main differences are that VIDC20 provides:
The VIDC20 has a 64 bit data bus allowing a high data bandwidth from memory. VIDC20 takes data from the memory banks under DMA control. VIDC20 takes its data from VRAM if it is fitted, otherwise it takes data from DRAM.
The VIDC 20 contains 296 write-only registers: 256 of these are used as the 28 bit video palette entries. Each entry uses 8 bits for Red, 8 bits for Green and 8 bits for Blue with 4 bits for external data.
The video palette entries or Look up tables (LUT) allow for logical to physical translation and gamma correction. The Red, Green and Blue LUTs each drive their respective DACs. These DACs give a total of 16 million possible colours.
VIDC20 can generate a display at any pixel rate up to at least 110Mhz. The clock can be selected from one of three sources, and then divided by a factor of between 1 and 8.
The VIDC20 also contains a phase comparator which - when used with an external Voltage Controlled Oscillator - forms a Phase Locked Loop. This allows a single reference clock to generate all the required frequencies for any display mode. You do not need multiple external crystals.
The sound system is compatible with the VIDC1 sound system with an independent sound clock (24MHz). It features an 8 bit (logarithmic) system using an internal DAC. This gives eight channels each with its own stereo position.
The device can work with 1, 2, 4 or 8 stereo channels using time division multiplexing to synthesise left and right outputs. The sample rate is programmable through the Sound Frequency Register.
VIDC20 has a hardware cursor for all its modes. The cursor is 32 pixels wide and any number of pixels high. Each pixel can be transparent, or one of three colours chosen from its own 28 bit wide palette. The cursor can be any shape or colour within these limits.
The IOMD is a specialised custom chip that takes the place of several large chips used in the old architecture.
IOMD includes some of the circuitry formerly in the IOC and MEMC chips, as well as a large amount of 'glue' logic.
The features of the IOMD include:
The IOMD is a memory, DMA and I/O controller.
It has a CPU interface for an ARM610/ARM700 type processor which can allow an additional processor to be connected. The CPU interface consists of the processor address, data and control buses.
There is a DRAM and VRAM control bus which has RAS, CAS, multiplexed address and other control lines. There are a number of DMA address generators, for sound, cursor, and general I/O DMA. There is also VRAM control logic, including logic to generate transfer cycles.
Since the whole 32 bits of the main system bus connects to IOMD, it is possible for IOMD to transfer data using DMA (Direct Memory Access) from DRAM into itself. There is a 16 bit I/O bus on IOMD, and there is byte (and half-word) steering logic to allow DMA data at arbitrary byte (or half-word) memory locations to be transferred to/from the I/O system using this bus. The 16 bit I/O bus forms the lower 16 bits of the 32 bit podule interface. IOMD controls the latches for the upper 16 bits of the extended podule bus, which allows 32 bit transfers.
IOMD contains a large subset of the functionality of IOC, including two general purpose counter/timers (timer 0 and timer 1) and the interrupt control registers. The IOC baud rate and keyboard serial rate timers are not implemented in IOMD, nor are all of the general purpose I/O lines. The allocation of interrupt lines is largely similar to previous machines.
IOMD provides a PC keyboard interface instead of the Archimedes KART interface supported by IOC. This consists of an 8 bit synchronous serial interface, with interrupt generation capability.
The chip contains a quadrature mouse interface. This consists of X and Y counters that are incremented and decremented by mouse movements. The counters wrap when they overflow or underflow, and are read regularly under interrupt. The VSync interrupt is used (although the centi-second timer could be used) as it allows updating every frame; there is no point in updating the screen more often than this. The X and Y counters are each 16 bits wide.
The ARM7500 is a monolithic device that integrates an ARM7 processor, a video generator similar to VIDC20, and most of the functions of IOMD. The major differences are:
The chapters that follow describe the changes introduced in RISC OS 3.5 and RISC OS 3.6. These changes are summarised below.