The OS_MMUControl SWI was updated for RISC OS 3.7 to add another reason code (reason code 1 to flush the cache). This has been extended with Kernel 9.80 to allow the write buffer to be drained. OS_MMUControl 0 has been extended to return errors if the MMU control register values are incompatible with the CPU or with the operating system.

OS_MMUControl (SWI &6B)
On entry
   R0 = operation and flags:
         bits 0-7  = operation
         bits 8-31 - flags
         Others dependant on operation
On exit
   Dependant on operation

This SWI is used to perform MMU operations. Consult the operation codes for more details.

OS_MMUControl 0
On entry
   R0 = 0 (set MMU control register) + flags :
         bits 0-7  = operation (1)
         bits 8-30 = reserved (must be zero)
         bit 31 = do not mirror D Cache bit into I Cache bit
   R1 = EOR value
   R2 = AND value
On exit
   R1 = old MMU control register value
   R2 = new MMU control register value

This SWI is used to change the state of the MMU control register in a processor independent manner. Any flags which are not changeable on the processor will return an error message. Any flags which are not changeable because the operating system does not support that configuration will return an error message.

For compatibility with earlier systems, unless bit 31 of the flags in R0 is set, the D cache bit will be mirrored into the I cache bit. If bit 31 of the flags in R0 is clear, the D cache bit will only control that one bit. For processors which do not provide an I cache, this has no effect.

OS_MMUControl 1
On entry
   R0 = 1 (cache and TLB operations) + flags :
         bits 0-7 = operation (1)
         bits 8-27 = reserved (must be zero)
         bit 28 = drain write buffer
         bit 29 = flush a single entry (otherwise a complete flush)
         bit 30 = flush processor TLBs
         bit 31 = flush processor cache (both I and D cache)
   R1 = logical address, if R0 bit 29 set 
On exit
   R0,R1 preserved

This call implements platform independent cache and/or TLB flushing.

Currently, bit 29 is ignored, so that only whole flushing of caches and/or TLBs are supported. A cache will be cleaned before flushing, where the processor supports a write-back cache.

This reason code is not re-entrant. Interrupts are not disabled during the flush, so the cache or TLB flush can only be considered to be complete with respect to logical addresses that are not currently involved in interrupts.

The 'drain write buffer' flag was introduced in Kernel 9.80.

This documentation is copyright 3QD Developments Ltd 2013 and may not be reproduced or published in any form without the copyright holders permission. RISC OS is subject to continuous development and improvement as such all information is reproduced by 3QD Developments Ltd in good faith and is believed to be correct at the time of publication E&OE. 3QD Developments Ltd cannot accept any liability for any loss or damage arising from the use of any information provided as part of the RISC OS Documentation.

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