The OS_PlatformFeatures SWI has been updated to provide additional information on the core system and the MMU.

OS_PlatformFeatures (SWI &6D)

Determine features of the host platform

On entry
   R0 = reason code and flags:
        bits 0-15  : reason code
        bits 16-31 : flags specific to reason
        Other registers dependant on reason code
On exit
   Registers dependant on reason code

This SWI is used to determine various features of the platform that the component is running on.

The particular action of OS_PlatformFeatures is given by the reason code in bits 0-15 of R0 as follows:

         0 = Read code features
         1 = Read MMU features
         other -  Reserved for future expansion
OS_PlatformFeatures 0

Read code features

On entry
   R0 = 0 (reason code) + flags (all reserved, must be 0)
On exit
   R0 = bit mask of features of the CPU and OS :
         bit 0 - Must tell OS when code areas change (by calling OS_SynchroniseCodeAreas)
         bit 1 - Enabling, then immediately disabling interrupts will not give interrupts a chance to occur (see R1)
         bit 2 - Must be in 32 bit mode to read hardware vectors
         bit 3 - Storing PC to memory (eg with STR or STM) stores PC+8 rather than PC+12
         bit 4 - Data aborts occur with 'full early' timing (i.e. as defined by ARM architecture 4)
         bit 5 - Reserved for future expansion
         bit 6 - Operating System executes in 32bit mode
         bit 7 - 26 bit mode is not available
         bits 8-31 - Reserved for future expansion
   R1 = pointer to routine to call to trigger IRQs after an enable (if bit 1 of R0 set)

This call was originally defined to determine features of the host processor's instruction set. It has been extended to return information about the Operating System's features as well.

Platforms running ARM 6 or 7 cores will return with R0 bits 0-4 clear. Platforms running StrongARM will return with bits 0, 1, 3 and 4 (RISC OS 3.7 incorrectly returns bit 2 set). Operating systems which are 32 bit will return with bit 6 set. ARM 6, 7 and StrongARM will return with bit 7 clear. Later ARM processors have abandoned 26 bit capabilities and bit 7 will be set. Consult the ARM Architecture Reference manual, or PRM 5a-15 for details of the distinction between 26 bit and 32 bit modes.

For compatibility with older versions of RISC OS, you should call this SWI in the X form; if the overflow flag (V) is set on return and the error is 'SWI not known', then this can be taken as equivalent to a return with R0 having all bits clear. Note that the easiest way to deal with the PC+8/PC+12 issue across all platforms is to make sure that the code is valid in either case (typically with judicious use of NOPs).

The routine pointed to by R1 is suitable for calling from any mode (26bit or 32bit); it preserves all flags and registers, and is reentrant.

OS_PlatformFeatures 1

Read MMU features

On entry
   R0 = 1 (reason code) + flags (all reserved, must be 0)
On exit
   R0 = default MMU state for cache enabled
   R1 = default MMU state for cache disabled
   R2 = acceptable flags for the MMU state (for the processor)
   R3 = required flags for the MMU state (for the processor)
   R4 = acceptable flags for the MMU state (for the OS)
   R5 = required flags for the MMU state (for the OS)

This call returns details about the Memory Management Unit features of the processor and the operating system. The flags returned are used by OS_MMUControl to determine the flags which it is acceptable for the user to modify. The flags in R2 and R4 are those which may be changed by the user. The flags in R3 and R5 are those which must be set for the system to function.

For example, certain processors allow the Instruction cache to be controlled and so that bit will be set within R2 (acceptable flags for the processor). The operating system is not affected by the state of the Instruction cache and can function with the flag in either state, thus R4 (acceptable flags for the OS) has this bit set. By contrast, some processors allow alignment faults to be raised by the processor and so this bit is set in R2. However the operating system cannot function in this mode, and the bit will be clear in R4.

Because of these restrictions there are a very limited set of changes which programs may make to the MMU state.

This documentation is copyright 3QD Developments Ltd 2013 and may not be reproduced or published in any form without the copyright holders permission. RISC OS is subject to continuous development and improvement as such all information is reproduced by 3QD Developments Ltd in good faith and is believed to be correct at the time of publication E&OE. 3QD Developments Ltd cannot accept any liability for any loss or damage arising from the use of any information provided as part of the RISC OS Documentation.

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